RV64 · Educational
CSRV64I_SC
Base educational core
A deliberately small RV64I core for learning instruction execution and building a verification baseline.
- RV64I base ISA
- Single-cycle datapath
- Machine mode
- No cache or MMU
- Readable SystemVerilog
CORESELVA OPEN IP
Six processor profiles. Three essential peripherals.
Explore the complete architecture roadmap without hiding families inside a carousel. Every card states whether it is implemented, planned, or research work.
RV64
RV64 cores
From a transparent single-cycle baseline to a pipelined FPGA core and a Linux-capable research direction.
Stable
RV64 · Pipelined
CSRV64I-P5
Five-stage FPGA core
A five-stage RV64I pipeline with visible hazard, forwarding, stall and flush behavior.
- IF/ID/EX/MEM/WB
- Hazard detection
- Forwarding paths
- Branch flush
- Artix-7 tested
RV64 · Research
CSRV64-GS-LX
Linux-capable research profile
The long-term path toward supervisor mode, Sv39, OpenSBI and a Linux-capable educational platform.
- RV64G target
- Supervisor mode
- Sv39 MMU
- OpenSBI
- Linux boot
Roadmap
RV32
RV32 cores
MCU-class profiles that progress from the base ISA into pipelining, multiply/divide, and compact code.
RV32 · Educational
RV32I_SC
Single-cycle educational core
A compact single-cycle core for learning MCU-class RISC-V fundamentals without pipeline complexity.
- RV32I base ISA
- Single-cycle datapath
- Machine mode
- FPGA-first design
- Small SoC focus
RV32 · Pipelined
CSRV32-IM
Pipelined MCU core
A 32-bit embedded profile that introduces pipelining, multiply/divide operations, and interrupts.
- RV32IM target
- Basic pipeline
- Interrupt support
- ASIC-ready direction
- Embedded workloads
Roadmap
RV32 · Compact
CSRV32-IMC
Compact MCU profile
A code-density-focused MCU roadmap profile for memory-constrained embedded systems.
- RV32IMC target
- Compressed instructions
- Interrupt support
- Low-memory systems
- SoC integration focus
Roadmap
Peripherals
SoC peripherals
Readable UART, GPIO, and Timer blocks intended to turn the processor cores into teachable systems.
SoC peripheral
UART
Serial communication IP
A readable transmit-and-receive block for teaching serial framing, buffering, status, and interrupts.
- TX and RX paths
- Configurable baud timing
- Status flags
- Interrupt-ready
- Simulation-first
Roadmap
SoC peripheral
GPIO
Digital input/output IP
A small memory-mapped GPIO block for switches, LEDs, external signals, and interrupt experiments.
- Input and output control
- Direction registers
- Bit-level access
- Edge interrupt direction
- Simulation-first
Roadmap
SoC peripheral
Timer
Timing and compare IP
A deterministic counter and compare block for timekeeping, periodic interrupts, and firmware scheduling.
- Free-running counter
- Compare events
- Periodic interrupt
- Memory-mapped control
- Simulation-first
Roadmap
STATUS LANGUAGE
Stable
Implemented and exercised on its stated target. Read the repository for exact verification scope.
Planned
A defined teaching direction, not yet a release claim.
Research
Longer-term architecture work whose interfaces and goals may change.