Open processor IP
Readable RV64 and RV32 RISC-V cores for education, FPGA experiments, verification, and architecture research.
RISC-V CORES · OPEN IP · EMBEDDED PERIPHERALS
CoreSelva builds open RISC-V cores, IP blocks, and peripherals — so engineers can read the silicon, not just trust it.
WHAT CORESELVA DOES
The work is focused on the layers that are often treated as black boxes.
Readable RV64 and RV32 RISC-V cores for education, FPGA experiments, verification, and architecture research.
UART, GPIO, Timer, and future peripheral IP designed to make complete systems understandable.
Long-form learning that starts from first principles and grows into embedded C, digital logic, RISC-V, FPGA, and verification.
OPEN IP
See the complete roadmap once, then open the family you need. Product cards, maturity, features, and source live in the catalogue.
From a transparent single-cycle baseline to a pipelined FPGA core and a Linux-capable research direction.
Explore RV64MCU-class profiles that progress from the base ISA into pipelining, multiply/divide, and compact code.
Explore RV32Readable UART, GPIO, and Timer blocks intended to turn the processor cores into teachable systems.
Explore PeripheralsCORESELVA ACADEMY
The Academy begins with no assumed programming or microcontroller experience, then develops the exact mental models needed for memory, registers, interrupts, buses, real-time firmware, processor architecture, and verification.
C, data, control flow, functions, and debugging
Memory, registers, interrupts, timing, and buses
Digital logic, RISC-V, pipelines, and SoCs
Simulation, verification, FPGA testing, and measurement
WHY CORESELVA
Read the story, the principles behind the work, and the long-term goal.