CSCoreSelva

RISC-V CORES · OPEN IP · EMBEDDED PERIPHERALS

Embedded systems deserve
open enough to build on.

CoreSelva builds open RISC-V cores, IP blocks, and peripherals — so engineers can read the silicon, not just trust it.

WHAT CORESELVA DOES

Hardware you can inspect. Knowledge you can build on.

The work is focused on the layers that are often treated as black boxes.

Open processor IP

Readable RV64 and RV32 RISC-V cores for education, FPGA experiments, verification, and architecture research.

Reusable SoC blocks

UART, GPIO, Timer, and future peripheral IP designed to make complete systems understandable.

Engineering education

Long-form learning that starts from first principles and grows into embedded C, digital logic, RISC-V, FPGA, and verification.

CORESELVA ACADEMY

Learn the software and the hardware as one system.

The Academy begins with no assumed programming or microcontroller experience, then develops the exact mental models needed for memory, registers, interrupts, buses, real-time firmware, processor architecture, and verification.

FROM CODE TO SILICON
  1. 01
    Programming

    C, data, control flow, functions, and debugging

  2. 02
    Embedded systems

    Memory, registers, interrupts, timing, and buses

  3. 03
    Computer architecture

    Digital logic, RISC-V, pipelines, and SoCs

  4. 04
    Engineering proof

    Simulation, verification, FPGA testing, and measurement

WHY CORESELVA

Make advanced hardware knowledge easier to enter, inspect, and extend.

Read the story, the principles behind the work, and the long-term goal.

About CoreSelva