Educational Hardware IP Design
Small, readable, and verified hardware IPs for education, research, and FPGA experimentation
Top-of-the-line 64-bit RISC-V cores designed for education and research
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Base Educational Core
Implemented / StableTeaching RISC-V fundamentals, verification baseline, architecture research starting point
Embedded / MCU Profile
Implemented / StableTeaching pipelined CPU design, embedded workloads, FPGA SoC integration
Linux / Research Profile
Long-term Research GoalAdvanced architecture research, OS-hardware interaction, Linux-capable RISC-V exploration
Empowering education, research, and innovation in hardware design
Undergraduate and postgraduate students learning CPU and SoC design
Educators teaching computer architecture and digital design
Academic researchers exploring hardware architecture
Early-stage companies prototyping embedded systems